Micron MTFDGAR1T4MAX-1AG13ABYY Fiche technique télécharger pdf (Page 5)

Architecture

The single-chip, Micron-developed ASIC controller, along with the host and Flash inter-

faces, provide an embedded ATA host bus adapter, a host/Flash translation layer, Flash

maintenance, channel control, and Flash RAID (RAIN) protection.

Flash endurance and reliability are optimized through the Flash maintenance features,

including static and dynamic wear leveling and RAIN protection. Most of these func-

tions are implemented directly within the controller hardware to optimize perform-

ance. The device is shipped in the configurations shown below.

Table 1: Configurations

User Capacity NAND Flash Process NAND Flash Density Package Count Die per BGA Package

700GB 25nm 32Gb 64 4

1.4TB 25nm 32Gb 64 8

Performance Specifications

Table 2: Performance Specifications

Notes 1–7 apply to entire table

Specification 700GB 1.4TB Unit

Sequential read 3.3 3.3 GB/s

Sequential write 600 630 MB/s

Random read 750,000 750,000 IOPS

Random write 50,000 95,000 IOPS

Random read/write (70/30) mixed workload 170,000 220,000 IOPS

READ latency <100 (MIN) <100 (MIN) µs

WRITE latency 13 (posted) (MIN) 13 (posted) (MIN) µs

Notes:

1. Drive is erased and filled with zeroes to achieve preconditioned state.

2. Performance results are with power limiting disabled. Contact Micron for more details

regarding performance values with power limiting enabled. Values derived from tests at

room temperature.

3. 128KB transfers are used for sequential read/write values; 4KB transfers are used for

random read/write values.

4. I/O performance numbers are measured in steady state using FIO with a preconditioned

drive under RHEL 6.3 with a queue depth of 256 and with raw device access on systems

with a single Intel Xeon E5-2667 2.90 GHz processor with 6 cores, 12 logical and hyper-

threading enabled.

5. Steady state performance is defined as conforming to the SNIA V1.0 Performance Test

Specification.

6. Latency performance numbers are measured using FIO with queue depth 1, random

transfer, 4KB transfer size for READ latency, 4KB transfer size for WRITE latency.

7. Performance numbers are notated in base 10.

P420m HHHL PCIe NAND SSD

Architecture

PDF: 09005aef853f2344

p420m_hhhl.pdf - Rev. O 8/2014 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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